AMD winds up Zen 6 cores for faster clock speeds

After teasing its 256-core Epycs for more than a year, AMD is finally ready to talk about architectural changes to the Zen core that not only make it possible, but will eventually power its next generation of Ryzen processors in desktop and mobile PCs.

During a press event in Las Vegas last week, AMD spilled the beans on its latest Zen cores, which promise an average 27 percent uplift in instructions per clock (IPC) across a variety of AI and server workloads, along with boosted clocks ranging from 4.1 to 5.3 GHz. We expect to see even higher frequencies on consumer chips before long, but AMD isn’t quite ready to talk about Ryzen just yet.

CPU performance is a function of power, IPC, and clocks, and with gains across all three, the cores are shaping up to be one of the company’s biggest generational jumps ever.

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A tale of two cores

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As in past Epyc launches, Zen 6 isn’t one core. It comes in two flavors: a frequency-optimized variant (Zen 6) and a density-optimized version (Zen 6c).

This split dates back to the launch of AMD’s Bergamo Epycs in 2023, which packed 128 compact Zen 4c cores into just eight chiplets. The chip’s debut drew comparisons to Intel’s still relatively new Efficient (E-cores) for obvious reasons. But under the hood, AMD’s Zen 4c was nothing like what Intel was doing. The core itself was nearly identical to Zen 4; it simply traded clocks and a bit of cache per core for a more densely packed CPU die.

The only difference between running an application on Bergamo or Genoa was how quickly it executed. The same could not be said of Intel’s P and E cores, which used different ISAs.

This remained a defining characteristic and advantage of AMD’s compact core architecture through Zen 5, which allowed it to ship Turin parts with up to 192 cores without users having to worry about whether their app was running on a compact core or not.

With Zen 6c, at least as we understand it, this philosophy is largely unchanged. Both Zen 6 and Zen 6c share the same ISA, with clock being the main differentiator. There are other micro-architectural differences between the two cores designed to balance IPC and clock speeds more effectively.

Looking at the core’s block diagram, this isn’t immediately obvious. Zen 6 and Zen 5 share a very similar front and backend.

We'd be tempted to call the core iterative if it weren't for the 20 to 31 percent IPC uplift for cloud and AI workloads that AMD claims over Zen 5. This suggests that core for core, a 4.1 GHz Zen 6c-based Venice Epyc should deliver performance on par with a Zen 5-based Turin Epyc running at 5 GHz.

That's a pretty sizable jump, but just because AMD is seeing generational performance uplift in enterprise server and cloud workloads doesn't mean we'll see the same gains on the client side. Many will recall the roughly 5 percent performance gains gaming PC enthusiasts reported with the Ryzen 9000-series, leading to the rather unfortunate turn of phrase "Zen 5 percent."

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That happened because game engines at the time simply weren't CPU-bottlenecked, and so faster cores could only raise the ceiling so much. Even so, AMD fellow and "Zen daddy" Mike Clark tells El Reg that PC buyers expect more than a 6 percent gain from Zen 6.

We're glossing over a bunch of low-level architectural optimizations here, but according to Clark, one of the biggest drivers of performance was to the front end. Zen 5 introduced a dual front end, which for simple workloads worked great, but lost a lot of steam when confronted with more dynamic loads.

"The Zen 6 team did a really good job for those larger footprint workloads that have a bipolar nature," Clark said. "It's not something that comes through. You're not going to see it in a block diagram very well. It's sort of subtle... but it's a big lever."

Another contributor was the move to a distributed scheduler in the out-of-order pipeline. One of the biggest performance drivers in modern CPU cores is that they don't execute instructions in the order they receive them. Instead, they reorder the instructions so as to keep the core's backend execution units fed with a constant stream of instructions.

This is where we see the biggest difference between Zen 6 and Zen 6c. To account for the slower clocks on the latter core, AMD gave the core's scheduler deeper queues, which Clark tells us helps with higher-latency workloads. Meanwhile, from what we understand, Zen 6's shallower queue enables it to clock higher on less power.

Finally, on the backend, AMD made several subtle changes which should have major implications for vector heavy workloads, including AI. One of the more significant was the ability to perform four AVX2 or two AVX-512 loads per cycle.

While this doesn't improve AVX-512 performance much, for applications that haven't been updated to use it, the core is now able to perform twice as many loads, which should improve throughput for legacy applications. This should come in handy, particularly on PCs, where Intel's outright lack of AVX-512 support has made AVX2 the lowest common denominator for a lot of software.

That's not to say AVX-512 didn't get some love this generation. For those running AI workloads on CPUs, Zen 6 now natively supports FP16 datatypes. Previously FP16 was supported, but required padding the data to FP32, which meant the lower precision didn't buy much in terms of performance. That's no longer the case in Zen 6.

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And while we're on the topic of AI acceleration, Clark notes that Zen 6 doubled the VNNI-INT8 pipes from two to four, and should effectively double throughput for workloads that support it.

Feeding the beast

While not strictly part of the core, AMD's Zen 6 processors also address one of the biggest asymmetries associated with its frequency and density optimized cores.

Going back to Bergamo, opting for a density-optimized Epyc didn't just come at the expense of clocks, but cache too. Each Zen 4c or Zen 5c chiplet contained twice as many cores, but the same amount of L3 cache.

With Zen 6 and Zen 6c, you may be giving up some clocks, but cache per core is now a constant 4 MB. As we discussed in a Venice deep dive back in September, each of the processor's eight CPU dies contain 12 or 32 cores and 48 and 128 MB respectively.

The benefit here is that users don't have to worry about different ISAs or cache hierarchies when optimizing their software stacks against AMD's Epyc processors. The same cannot be said of Intel's Xeon processors.

As we alluded to earlier, Chipzilla's performance and efficiency cores use different micro-architectures, ISAs, cache hierarchies, clocks, and even cluster their cores differently. This can pose real headaches if you have workloads that take advantage of fat vector registers like AVX-512, or accelerators like AMX, which will work just fine on Intel's P-cores but won't even run on their E-cores.

This, along with support for SMT (Hyperthreading), which Intel has dropped for now, could help the House of Zen vacuum up even more market share from its long-time rival. ®