AMD's Epyc X-chips are back after a three-year hiatus

AMD's cache-packed Epyc X chips are officially making a comeback.

Based on the House of Zen's frequency-optimized SKUs we looked at back in September, its HPC-optimized Venice-X parts will offer up to 96 cores and use the company's 3D V-Cache chip stack tech to triple the L3 cache density to more than a gigabyte.

But before you get too excited about another cache-packed Epyc, it'll be a little while before they actually ship. AMD expects the Venice-X to begin trickling out in the second half of 2027.

REG AD

First teased at CES earlier this year, the chips are primarily aimed at latency-sensitive technical and scientific computing workloads like computational fluid dynamics and electronic design automation (EDA).

REG AD

AMD itself relies heavily on its X-series Epycs for EDA workloads like functional verification testing, which is used to simulate silicon in order to ensure it behaves as it's intended to. According to AMD Fellow Phil Steinke, by keeping more of the model in cache, the CPU cores don't have to wait as long for data to move in and out of system memory.

Normally, boosting L3 capacity would have required larger chiplets with lower yields, but that's not how AMD has gone about it for the past four years. Instead, it used advanced packaging to give its existing CPU dies a little SRAM backpack.

This tech has been around for several generations now, having first debuted in the Ryzen 7 5800X3D back in 2022. That consumer desktop chip stacked a 64 MB SRAM tile on top of an 8-core chiplet, boosting L3 capacity to 96 MB. The extra cache made the chip one of the most potent gaming CPUs of the time.

Later that year, AMD brought the same technology to its Milan generation of Epycs as the company expanded its portfolio to address a wider range of workloads. The extra cache was popular enough to justify a second generation of X-series Epycs, which launched in 2023.

But then, nothing. When AMD unveiled its 5th-gen Epycs in late 2024, there was no Turin-X on the roadmap.

According to Madhu Rangarajan, who runs AMD's compute and enterprise AI products biz, this was intentional. "We are not doing the X every generation.... The enterprise HPC kind of market tends to have a cadence that's a little bit slower, so that's what drives our cadence."

Venice-X marks the return of AMD's X-chips, and for the most part, the processor largely follows the same recipe as its predecessors. Each of the chip's up to eight CPU dies is now bonded to a 96 MB SRAM tile using advanced packaging, for a total of 144 MB of L3 per chiplet or 1,152 MB per socket, which you might have noticed is the same as in the Genoa-X parts they replace.

But while core count and cache capacity haven't increased, clock speeds certainly have, with Venice now hitting 5.3 GHz compared to Genoa-X at just 3.7 GHz.

REG AD

"In Milan and Genoa, there was one trade-off. You either had to choose something that was high frequency or you chose something with 3D V-Cache." HPC likes both, Rangarajan told El Reg.

The method for integrating the SRAM tile required this kind of compromise. Stacking SRAM on top of the compute chiplets boosted L3 caches, but also trapped heat, which limited boost clocks.

So, for the Zen 5 generation, AMD moved the SRAM tile from the top of the stack to the bottom. With the SRAM tile no longer acting as a blanket, the chips could run hotter and faster for longer. But while gamers enjoyed the higher clocks and bigger caches on AMD's Ryzen 9000 processors, only now with Venice-X are those improvements making their way into Epyc.

Because customers no longer have to choose between big caches and fast clocks, Rangarajan believes the chip may see wider adoption. "I think it's going to end up being much bigger in HPC than the previous generations where we had to make that tradeoff."

Curiously, if frequency weren't such a high priority, Venice-X may not have needed 3D stacked SRAM in the first place. As we reported earlier this year, AMD's top-specced Venice CPUs boast 256 cores and 1,024 MB of L3 cache.

AMD could have just fused off 160 of the cores and achieved a similar cache-per-core ratio. In fact, AMD did something like this for the Turin generation: For the Epyc 9175F, AMD essentially took a 128-core part and fused off 112 of the cores. What was left was a 16-core part with 512 MB of last-level cache.

"You could do that [with Venice], but then you don't get the frequency part of it. The Fmax would be at 4.1 gigahertz and not 5.3 GHz," Rangarajan said. 

"Venice X really changes the game," he added. "For the first time, you can get the larger L3 in our highest frequency part." ®